A 140-Mb/s, 32-state, radix-4 Viterbi decoder

This publication has 14 references indexed in Scilit:

• Stanford Telecom VLSI design of a convolutional decoder
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Algorithms and architectures for concurrent Viterbi decoding
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A block processing method for designing high-speed Viterbi detectors
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Generalized trace back techniques for survivor memory management in the Viterbi algorithm
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures
  IEEE Journal of Solid-State Circuits, 1991
• High-speed CMOS circuit technique
  IEEE Journal of Solid-State Circuits, 1989
• An alternative to metric rescaling in Viterbi decoders
  IEEE Transactions on Communications, 1989
• Locally connected VLSI architectures for the Viterbi algorithm
  IEEE Journal on Selected Areas in Communications, 1988
• Memory Management in a Viterbi Decoder
  IEEE Transactions on Communications, 1981
• Viterbi Decoding for Satellite and Space Communication
  IEEE Transactions on Communication Technology, 1971