A Self-Testing Dynamic RAM Chip
- 1 February 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (1) , 428-435
- https://doi.org/10.1109/JSSC.1985.1052325
Abstract
A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.Keywords
This publication has 8 references indexed in Scilit:
- A submicron VLSI memory with a 4b-at-a-time built-in ECC circuitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 64K FET Dynamic Random Access Memory: Design Considerations and DescriptionIBM Journal of Research and Development, 1980
- Testing Memories for Single-Cell Pattern-Sensitive FaultsIEEE Transactions on Computers, 1980
- A survey of high-density dynamic RAM cell conceptsIEEE Transactions on Electron Devices, 1979
- Leakage studies in high-density dynamic MOS memory devicesIEEE Journal of Solid-State Circuits, 1979
- An integrated test concept for switched-capacitor dynamic MOS RAM'sIEEE Journal of Solid-State Circuits, 1977
- Detection oF Pattern-Sensitive Faults in Random-Access MemoriesIEEE Transactions on Computers, 1975
- A Simple Self-Testing Decoder Checking CircuitIEEE Transactions on Computers, 1971