MOSAIC V-a very high performance bipolar technology
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors describe the initial implementation of MOSAIC V (Motorola oxide isolated self-aligned implanted circuits, fifth generation), a novel silicon process technology. A number of innovative process approaches and novel methods of aggressive device scaling result in deep submicron device structures in the range of 0.1-0.4 mu m. A very low speed-power product of 92 fJ at 3.3-V supply voltage for ECL (emitter coupled logic) gates is obtained in the lower range of operating currents, with typical gate delays of 73 ps at 100 mu A and 35 ps at 800 mu A switch currents. Using a selectively implanted collector, a minimum ECL gate delay of 29 ps at 800 mu A switch current is achievable.<>Keywords
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