A study of deep-submicron MOSFET scaling based on experiment and simulation
- 1 April 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 42 (4) , 669-677
- https://doi.org/10.1109/16.372070
Abstract
The scaling relationships among three fundamental quantities of deep-submicron MOSFET's, i.e., effective channel length Leff, device speed gm/WCox, and drain-induced barrier lowering (DIBL) δVt/δVds, are investigated using both device measurements and numerical simulations. It is found that these relationships can be expressed in power-law forms with excellent statistical significance for both experimental and simulation data samples. The dependence of these scaling relationships on two sets of device parameters is also investigated experimentally and confirmed by numerical simulations. These two sets of parameters are: 1) channel parameters-gate oxide thickness tox threshold voltage Vt, and channel doping profile; and 2) source/drain parameters-junction depth xj, parasitic resistance Rsd , and junction abruptness (e.g., “halo” doping structure). In the deep-submicron regime with Leff from 0.5 μm down to sub-0.1 μm, it is found that certain relationships among the three fundamental quantities are insensitive or “universal” with respect to particular subsets of device parameters. The relationship between gm/WCox and δVt/δVds with Leff as an implicit variable is found to be insensitive to tox, Vt , and channel doping profile within their respective experimental ranges. The trade-off between device performance (represented by gm /WCox) and short channel effect (represented by δVt/δVds) is dominated by source/drain parameters xj, Rsd and junction abruptness, rather than channel parameters tox, Vt and channel doping profile. Also, the power coefficient relating δVt/δVds, to Leff is found to be insensitive to tox, Vt, and channel dopingKeywords
This publication has 22 references indexed in Scilit:
- High performance 0.1 μm CMOS devices with 1.5 V power supplyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Room temperature 0.1 μm CMOS technology with 11.8 ps gate delayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Silicon MOS transconductance scaling into the overshoot regimeIEEE Electron Device Letters, 1993
- High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technologyIEEE Transactions on Electron Devices, 1993
- An improved generalized guide for MOSFET scalingIEEE Transactions on Electron Devices, 1993
- High Performance 0.1/spl mu/m nMOSFET's with 10 ps/stage Delay (85 K) at 1.5 V Power SupplyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- A new method to determine MOSFET channel lengthIEEE Electron Device Letters, 1980
- MINIMOS—A two-dimensional MOS transistor analyzerIEEE Transactions on Electron Devices, 1980
- A New Method to Determine Effective MOSFET Channel LengthJapanese Journal of Applied Physics, 1979