High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

This publication has 14 references indexed in Scilit:

• An integrated 0.5 mu m CMOS disposable TiN LDD/salicide spacer technology
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A new half-micron p-channel MOSFET with LATIPS (large-tilt-angle implanted punchthrough stopper)
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Design guidelines for deep-submicrometer MOSFETs
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A high-performance 0.25- mu m CMOS technology. II. Technology
  IEEE Transactions on Electron Devices, 1992
• A high-performance 0.25- mu m CMOS technology. I. Design and characterization
  IEEE Transactions on Electron Devices, 1992
• Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's)
  IEEE Electron Device Letters, 1992
• KrF excimer laser lithography technology for 64M DRAM.
  Journal of Photopolymer Science and Technology, 1991
• Thermally Stable, Low‐Leakage Self‐Aligned Titanium Silicide Junctions
  Journal of the Electrochemical Society, 1990
• SMART-P: rigorous three-dimensional process simulator on a supercomputer
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
• A half micron MOSFET using double implanted LDD
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1982