The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes
- 1 March 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 45 (3) , 665-679
- https://doi.org/10.1109/16.661228
Abstract
In oxide chemical-mechanical polishing (CMP) pro- cesses, layout pattern dependent variation in the interlevel di- electric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation spec- ification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial- based experiments demonstrate the beneficial impact of metal- fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices—grounded versus floating metal—are explored. Crite- ria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.Keywords
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