A yield improvement technique for IC layout using local design rules

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Vol. 11 (11) , 1355-1362
https://doi.org/10.1109/43.177399

Abstract

The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples

Keywords

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