A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structure
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 115-118
- https://doi.org/10.1109/iedm.1990.237213
Abstract
A 3.6 mu m/sup 2/ 5 V only 16 Mb flash EEPROM cell was obtained using a simple stacked gate structure and a conventional 0.6 mu m CMOS process. A single 5 V power supply operation of the simple stacked gate cell was realized by optimizing the well impurity concentration and the drain structure and using a gate negative biased erasing operation. It is also shown that the gate negative biased erasing operation mode is very effective in improving the cell endurance characteristics.<>Keywords
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