A programmable BIST architecture for clusters of multiple-port SRAMs
- 8 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 557-566
- https://doi.org/10.1109/test.2000.894249
Abstract
This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.Keywords
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