A general index mapping technique for array reconfiguration
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 559-563
- https://doi.org/10.1109/iscas.1988.14988
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Fast Algorithms for Bipartite Network FlowSIAM Journal on Computing, 1987
- Reconfigurable architectures for VLSI processing arraysProceedings of the IEEE, 1986
- Fault Tolerance Techniques for Array Structures Used in SupercomputingComputer, 1986
- Wafer-Scale Integration of Systolic ArraysIEEE Transactions on Computers, 1985
- Configuration of VLSI Arrays in the Presence of DefectsJournal of the ACM, 1984
- The Diogenes Approach to Testable Fault-Tolerant Arrays of ProcessorsIEEE Transactions on Computers, 1983
- An O(|V|3) algorithm for finding maximum flows in networksInformation Processing Letters, 1978