Asynchronous embryonics
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 201-210
- https://doi.org/10.1109/eh.2001.937963
Abstract
As embryonic arrays take inspiration from nature they display biological properties, namely complex structure and fault-tolerance. However, they have yet to take advantage of a further biological feature at a fundamental level; asynchronous operation. In addition to the benefits normally associated with asynchronous digital design, such as intrinsic power management, two areas in which embryonic arrays could benefit are scalability and reliability. This paper gives an overview of embryonic systems and a pertinent asynchronous methodology, that of macromodules. It is shown that a macromodule approach allows the implementation of asynchronous circuits on Xilinx Virtex FPGAs using only the standard design tools. A preliminary VHDL simulation illustrates the operation of an asynchronous embryonic array. Although mentioned, little detail of the reconfiguration scheme is given for brevity. This simulation brings truly asynchronous embryonic circuits a step closer.Keywords
This publication has 9 references indexed in Scilit:
- AMULET3: a 100 MIPS asynchronous embedded processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Embryonics+immunotronics: a bio-inspired approach to fault tolerancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Toward robust integrated circuits: The embryonics approachProceedings of the IEEE, 2000
- Analysis of unconventional evolved electronicsCommunications of the ACM, 1999
- Field programmable processor arraysPublished by Springer Nature ,1998
- Phylogeny, ontogeny, and epigenesis: Three sources of biological inspiration for softening hardwarePublished by Springer Nature ,1997
- Asynchronous design methodologies: an overviewProceedings of the IEEE, 1995
- Using FPGAs to implement self-timed systemsJournal of Signal Processing Systems, 1993
- Four state asynchronous architecturesIEEE Transactions on Computers, 1992