SEU-tolerant SRAM design based on current monitoring
- 1 January 1994
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 106-115
- https://doi.org/10.1109/ftcs.1994.315652
Abstract
ISBN: 0818655208We present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on the SRAM columns and it is combined with a single-parity bit per RAM word to perform error correctionKeywords
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