Test generation for current testing (CMOS ICs)
- 1 February 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 7 (1) , 26-38
- https://doi.org/10.1109/54.46891
Abstract
Current testing is useful for testing CMOS ICs because it can detect a large class of manufacturing defects, including defects that traditional stuck-at fault testing misses. The effectiveness of current testing can be enhanced if built-in current sensors are applied on-chip to monitor defect-related abnormal currents in the power supply buses. Such sensors have proved effective for built-in self-test. However, current testing requires the use of a special method to generate test vectors. The authors describe this method, which differs from that for traditional voltage-oriented testing, and postulate a test-generation algorithm for both on-chip and off-chip current testing. The algorithm uses realistic fault models extracted directly from the circuit layout.Keywords
This publication has 15 references indexed in Scilit:
- Electrical properties and detection methods for CMOS IC defectsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Layout-driven test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Built-in current testing-feasibility studyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A self-testing ALU using built-in current sensingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- COSMOS: a compiled simulator for MOS circuitsPublished by Association for Computing Machinery (ACM) ,1987
- Yield Simulation for Integrated CircuitsPublished by Springer Nature ,1987
- Test Considerations for Gate Oxide Shorts in CMOS ICsIEEE Design & Test of Computers, 1986
- Inductive Fault Analysis of MOS Integrated CircuitsIEEE Design & Test of Computers, 1985
- An O (N log N) Algorithm for Boolean Mask OperationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978