An efficient design environment and algorithms for transport processing FPGA
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We introduce a CAD system for the original FPGA "PROTEUS", which has several features suitable for the efficient realization of practical digital transport processing systems. These features are considered in the design of the CAD system. Our CAD system supports both automatic and manual design environments. The automatic design environment offers complete top down design from high level hardware description to downloading the programming data into the FPGA. In the manual design environment, an interactive chip editor is provided that enables high performance circuits to be constructed skillfully. The paper introduces our design strategy and the algorithms that realize them.Keywords
This publication has 12 references indexed in Scilit:
- PROTEUS: programmable hardware for telecommunication systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Performance directed synthesis for table look up programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A speed-up technique for synchronous circuits realized as LUT-based FPGAsPublished by Springer Nature ,1994
- FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Synthesis method for field programmable gate arraysProceedings of the IEEE, 1993
- BDD based decomposition of logic functions with application to FPGA synthesisPublished by Association for Computing Machinery (ACM) ,1993
- Field-Programmable Gate ArraysPublished by Springer Nature ,1992
- VLSI cell placement techniquesACM Computing Surveys, 1991
- Chortle-crf: Fast technology mapping for lookup table-based FPGAsPublished by Association for Computing Machinery (ACM) ,1991
- Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiencyIEEE Journal of Solid-State Circuits, 1990