Procedures for static compaction of test sequences for synchronous sequential circuits
- 1 June 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 49 (6) , 596-607
- https://doi.org/10.1109/12.862219
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Compaction of ATPG-generated test sequences for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- HITEC: a test generation package for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Static test sequence compaction based on segment reordering and accelerated vector restorationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- State relaxation based subsequence removal for fast static compaction in sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restorationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Vector restoration based static compaction of test sequences for synchronous sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast static compaction algorithms for sequential circuit test vectorsIEEE Transactions on Computers, 1999
- Sequential circuit test generation in a genetic algorithm frameworkPublished by Association for Computing Machinery (ACM) ,1994
- CRIS: A test cultivation program for sequential VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Gentest: an automatic test-generation system for sequential circuitsComputer, 1989