State relaxation based subsequence removal for fast static compaction in sequential circuits
- 27 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 577-582
- https://doi.org/10.1109/date.1998.655916
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Automatic test generation using genetically-engineered distinguishing sequencesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Simulation-based techniques for dynamic test sequence compactionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- HITEC: a test generation package for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sequential circuit test generation using dynamic state traversalPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Acceleration techniques for dynamic vector compactionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast static compaction algorithms for sequential circuit test vectorsIEEE Transactions on Computers, 1999
- On static compaction of test sequences for synchronous sequential circuitsPublished by Association for Computing Machinery (ACM) ,1996
- Test compaction for sequential circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992