On the design of a redundant programmable logic array (RPLA)
- 1 February 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (1) , 114-117
- https://doi.org/10.1109/jssc.1987.1052682
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
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- A Hi-CMOSII 8Kx8 bit static RAMIEEE Journal of Solid-State Circuits, 1982
- A Design of Programmable Logic Arrays with Universal TestsIEEE Transactions on Computers, 1981
- Multiple Fault Detection in Programmable Logic ArraysIEEE Transactions on Computers, 1980
- A fault-tolerant 64K dynamic random-access memoryIEEE Transactions on Electron Devices, 1979
- Multiple word/bit line redundancy for semiconductor memoriesIEEE Journal of Solid-State Circuits, 1978
- An Introduction to Array LogicIBM Journal of Research and Development, 1975