Design and verification of clock distribution in VLSI

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Abstract
Some of the design considerations involved in producing a circuit with minimal clock skew are described. The use of the electron beam probe for verifying the effectiveness of the resulting implementation is also described. The electron beam probe allows utilization of the voltage contrast effect for measuring timing relationships between clock signals as they are distributed throughout a VLSI device. An example is shown which demonstrates subnanosecond synchronization of such signals. Another example shows how a combination of marginal design practices and slight processing deviations can lead to significant internal clock skew and device failure. The approach described provides accurate measurement of the timing relationships between internal clock signals without disrupting the physical environment surrounding the probed node or otherwise distorting the edge placement of the signals during the measurement.

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