Clock distribution strategies for WSI: a critical survey
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors review the available methods for clock distribution design which have been used at the VLSI level and discuss the adjustments necessary for WSI (wafer scale integration) design. It is pointed out that much work has been reported regarding methods for clock distribution design for VLSI, and it is noted that these techniques can be applied to WSI with appropriate adjustments made for longer signal paths, higher capacitance, higher resistance, and higher fanout. The added complexity of potential alternate paths and associated alternate RC values must be considered when restructurable WSI circuits are clocked at high frequency. Resistance associated with the discretionary link process can make a significant contribution to the relevant delay calculations.Keywords
This publication has 16 references indexed in Scilit:
- Power distribution for highly parallel WSI architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A deterministic algorithm for automatic CMOS transistor sizingIEEE Journal of Solid-State Circuits, 1988
- Optimization-based transistor sizingIEEE Journal of Solid-State Circuits, 1988
- An elastic pipeline mechanism by self-timed circuitsIEEE Journal of Solid-State Circuits, 1988
- A safe single-phase clocking scheme for CMOS circuitsIEEE Journal of Solid-State Circuits, 1988
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983
- A programmable NMOS DRAM controller for microcomputer systems with dual-port memory and error checking and correctionIEEE Journal of Solid-State Circuits, 1983
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982
- A synchronous approach for clocking VLSI systemsIEEE Journal of Solid-State Circuits, 1982
- Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systemsIEEE Transactions on Electron Devices, 1979