Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits
- 1 March 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 9 (3) , 329-331
- https://doi.org/10.1109/43.46808
Abstract
A sequence of input vectors which detects all transistor stuck-open faults in a CMOS combinational circuit is a complete test sequence. Given a complete set of two-pattern tests for transistor stuck-open faults in a CMOS circuit, it is shown that a complete test sequence of minimum length can be obtained efficiently. A precise description of this problem and examples to illustrate the method are presentedKeywords
This publication has 10 references indexed in Scilit:
- The complexity of generating minimum test sets for PLA's and monotone combinational circuitsIEEE Transactions on Computers, 1989
- On the complexity of computing tests for CMOS gatesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic CircuitsIEEE Transactions on Computers, 1986
- Modeling and Test Generation Algorithms for MOS CircuitsIEEE Transactions on Computers, 1985
- A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault DetectionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- On Fault Detection in CMOS Logic NetworksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980
- On finding minimal length superstringsJournal of Computer and System Sciences, 1980
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976