Floating-point nonlinear DSP coprocessor cell-two cycle chip
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Implementation of systolic arrays has been hindered in the past due to a lack of building blocks, or cells. This paper presents a high-speed floating-point DSP coprocessor cell for rapid computation of nonlinear functions. Several nonlinear functions are typically needed in systolic arrays for signal and image processing algorithms, while the development costs as well as interconnection considerations warrant the use of only a few types of cells. With our approach all of the nonlinear functions needed can be incorporated on a single cell. Furthermore, a new result is produced every two clock cycles in a pipeline mode. The underlying principle which has made the combined goals of high-speed and multi-functionality possible, is significance-based second order interpolation of very small ROM tables. A 32 bit two-cycle chip for computing the square-root, fabricated in 2.0 micron CMOS technology, is presented. As an application example, a parallel architecture for CT image reconstruction for a Fan Beam CT System is briefly discussed.Keywords
This publication has 14 references indexed in Scilit:
- A WSI rapid prototyping architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Image processing using a universal nonlinear cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Square-root, reciprocal, sine/cosine, arctangent cell for signal and image processingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Complex-argument universal nonlinear cell for rapid prototypingIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
- Distributed resetIEEE Transactions on Computers, 1994
- Parallel architecture for universal digital signal processingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1994
- Parallel processing architectures for advanced signal processingMicroprocessors and Microsystems, 1992
- An architecture for WSI rapid prototypingComputer, 1992
- Design and programming of a flexible, cost-effective systolic array cell for digital signal processingIEEE Transactions on Acoustics, Speech, and Signal Processing, 1990
- Minimum Mean Running Time Function Generation Using Read-Only MemoryIEEE Transactions on Computers, 1983