Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture
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- 6 February 2002
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 46 (3) , 373-378
- https://doi.org/10.1016/s0038-1101(01)00111-3
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- On the subthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFETsSolid-State Electronics, 1999
- Capacitance Network Model of the Short Channel Effect for 0.1 µm Fully Depleted SOI MOSFETJapanese Journal of Applied Physics, 1996
- Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET'sIEEE Transactions on Electron Devices, 1995
- Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technologyIEEE Transactions on Electron Devices, 1995
- Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate lengthIEEE Transactions on Electron Devices, 1993
- Threshold voltage model for deep-submicrometer MOSFETsIEEE Transactions on Electron Devices, 1993
- Two-dimensional analytic modeling of very thin SOI MOSFETsIEEE Transactions on Electron Devices, 1990