CMOS scan-path IC design for stuck-open fault testability
- 1 October 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (5) , 880-885
- https://doi.org/10.1109/jssc.1987.1052828
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- CMOS circuit testabilityIEEE Journal of Solid-State Circuits, 1986
- Design of Testable CMOS Logic Circuits Under Arbitrary DelaysIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault DetectionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Test Generation for MOS Circuits Using D-AlgorithmPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Design for Autonomous TestIEEE Transactions on Computers, 1981
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978