Electrical properties of metal-SiO2-silicon structures under mechanical stress

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Abstract
The processing of integrated circuits usually introduces mechanical stress into the device structure. Contradictory results and speculations exist in the literature on the effects of such stresses on the electrical properties of the SiO2–Si interface. Results of three series of experiments in which the electrical properties were measured by MOS capacitance‐voltage methods are reported. Stress was applied at the SiO2–Si interface by deposition of stressed tungsten films. In the first experiments, the stress at the SiO2–Si interface was varied by deposition techniques and heat treatments. Although several such experiments are reported in the literature, our results demonstrate that such experiments invariably lead to ambiguous results and interpretation. A second series of experiments in which the metallization thickness was varied by planar etching, and a third series in which metallization patterns of widely differing geometries, from 5 to 500 μm were used, separately show conclusively that mechanical stresses in the range encountered in device structures do not affect the electrical properties of the SiO2–Si interface.