VLSI Architecture for an adaptive equalizer in ISDN line termination
- 24 March 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 11, 1525-1528
- https://doi.org/10.1109/icassp.1986.1168556
Abstract
VLSI architecture for an Adaptive equalizer needed to provide digital subscriber line transmission at hundreds of kbits/s is described. A wide AGC dynamic range, and quick adjustment of the filter coefficients are required for precise adaptive equalization. Considering the advances in VLSI technology, a single-chip multi-processor VLSI, composed of a high-speed filtering processor, control processors, analog-to-digital converter, and digital phase-locked loop (DPLL) is proposed. All processors are synchronized by the internal DPLL. The performance of the key components, developed using 1.5µm CMOS technology, shows that a fully integrated CMOS VLSI capable of implementing all functions of an adaptive equalizer is entirely feasible.Keywords
This publication has 4 references indexed in Scilit:
- A 160kb/s full duplex digital echo canceling transceiverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A CMOS adaptive line equalizerIEEE Journal of Solid-State Circuits, 1984
- A CMOS automatic line equalizer LSI chip using active-RC filteringIEEE Journal of Solid-State Circuits, 1984
- A CMOS switched capacitor variable line equalizerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983