Limitations of switch level analysis for bridging faults
- 1 July 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 8 (7) , 807-811
- https://doi.org/10.1109/43.31538
Abstract
Switch-level models are widely used for fault analysis of MOS digital circuits. Switch-level analysis (SLA) provides significantly more accurate results compared to gate-level models, and also avoids the complexities of circuit-level analysis. The accuracy of SLA is critically examined, and conditions under which SLA may generate incorrect results are specified. Such conditions may occur when the bulk of a transistor is connected to its source. These conditions are especially applicable under certain types of bridging faults. A simple technique is suggested for accurate switch-level modeling under such conditionsKeywords
This publication has 7 references indexed in Scilit:
- Considerations for the design of an SRAM with SOI technologyIEEE Circuits and Devices Magazine, 1987
- Anomalous subthreshold current—Voltage characteristics of n-channel SOI MOSFET'sIEEE Electron Device Letters, 1987
- On accuracy of switch-level modeling of bridging faults in complex gatesPublished by Association for Computing Machinery (ACM) ,1987
- Improved subthreshold characteristics of n-channel SOI transistorsIEEE Electron Device Letters, 1986
- A Fault Simulation Methodology for VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Charge pumping in SOS—MOS transistorsIEEE Transactions on Electron Devices, 1981
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980