An ECL 100K-compatible 1024x4 bit RAM with 15 ns access time
- 1 October 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (5) , 850-854
- https://doi.org/10.1109/jssc.1979.1051283
Abstract
An ECL 100K-compatible 1024/spl times/4 bit RAM with 15 ns access time, 900 mW power dissipation, and a chip size of 18.3 mm/SUP 2/ has been developed for caches and control memories of high-performance computer systems. The 1K/spl times/4 organisation mode combines the lower cost per bit of a 4K-bit device with the higher memory-module design flexibility of a 1K word unit. The excellent speed performance together with the high packing density have been achieved by using an oxide isolation technology with oxide-walled emitters in conjunction with novel circuit techniques.Keywords
This publication has 4 references indexed in Scilit:
- A high-speed low-power 4096 x 1 bit bipolar RAMIEEE Journal of Solid-State Circuits, 1978
- A masterslice LSI for subnanosecond random logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- A 4096 x 1 static bipolar RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- A 1024-bit ECL RAM with 15-ns access timePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1976