Unfolding and retiming for high-level DSP synthesis
- 1 January 1991
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Digit-serial DSP architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A systematic approach for design of digit-serial signal processing architecturesIEEE Transactions on Circuits and Systems, 1991
- Static rate-optimal scheduling of iterative data-flow programs via optimum unfoldingIEEE Transactions on Computers, 1991
- Dedicated DSP architecture synthesis using the MARS design systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- The high-level synthesis of digital systemsProceedings of the IEEE, 1990
- Force-directed scheduling for the behavioral synthesis of ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Algorithm transformation techniques for concurrent processorsProceedings of the IEEE, 1989
- Synchronous data flowProceedings of the IEEE, 1987
- Parallel Sequencing and Assembly Line ProblemsOperations Research, 1961