A Path Delay Fault Simulator for Sequential Circuits
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 269-274
- https://doi.org/10.1109/icvd.1993.669695
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- A New Method for Generating Tests for Delay Faults in Non-Scan CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Delay test generation for synchronous sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Delay fault models and test generation for random logic sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- DynaTAPP: dynamic timing analysis with partial path activation in sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- PROOFS: a fast, memory-efficient sequential circuit fault simulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Differential fault simulation for sequential circuitsJournal of Electronic Testing, 1990
- On Delay Fault Testing in Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987