Performance analysis of a system of communicating processes
- 1 January 1997
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Efficient exploration of the system design space necessitates fast and accurate performance estimation as opposed to the computationally prohibitive alternative of exhaustive simulation. The paper addresses the issue of worst case performance analysis of a system described as a set of concurrent communicating processes. We show that the synchronization overhead associated with inter process communication can contribute significantly to the overall system performance. Application of existing performance analysis techniques, which target single process descriptions, lead to inaccurate performance estimates as the synchronization overhead is not accounted for. We present PERC, a fast and accurate worst case performance analysis technique which analyzes inter process communication, and accounts for synchronization overhead while computing the worst case performance estimate of a given system implementation. Application of PERC to example systems described as multiple communicating processes shows the ability of the proposed method to accurately estimate the worst case performance of the system implementation.Keywords
This publication has 11 references indexed in Scilit:
- Efficient software performance estimation methods for hardware/software codesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- The Princeton University behavioral synthesis systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- System clock estimation based on clock slack minimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Analysis of multi-process VHDL specifications with a Petri net modelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast true delay estimation during high level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
- Formulation and evaluation of scheduling techniques for control flow graphsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1995
- Performance analysis and optimization of schedules for conditional and loop-intensive specificationsPublished by Association for Computing Machinery (ACM) ,1994
- Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994
- Timing analysis in high-level synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Chippe: a system for constraint driven behavioral synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990