Bottom-up methodology for test preparation and refinement
- 13 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A bottom-up testing methodology is used to derive realistic fault lists (at layout level), to refine gate-level test patterns, and to provide accurate test validation (at switch-level), thus making possible the evaluation of the fault coverage of the most likely circuit faults. For this purpose, the developed software tools, which are integrated in the ICD toolbox, are described, and their usefulness is ascertained through several design examples. Interesting spin-offs of the proposed methodology and directions of future work are also described.Keywords
This publication has 7 references indexed in Scilit:
- Test preparation and fault analysis using a bottom-up methodologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fault modeling and test algorithm development for static random access memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Bottom-up testing methodology for VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Realistic fault modeling for VLSI testingPublished by Association for Computing Machinery (ACM) ,1987
- A Multivalued Algebra For Modeling Physical Failures in MOS VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Modeling and Test Generation Algorithms for MOS CircuitsIEEE Transactions on Computers, 1985
- Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their TestabilityIEEE Transactions on Computers, 1980