A high performance 0.35 μm logic technology for 3.3 V and 2.5 V operation
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- High-performance devices for a 0.15- mu m CMOS technologyIEEE Electron Device Letters, 1993
- High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technologyIEEE Transactions on Electron Devices, 1993
- An ultra-shallow buried-channel PMOST using boron penetrationIEEE Transactions on Electron Devices, 1993
- Sub-Quarter-Micron PMOSFETs With Shallow Source And Drain Formed By Rapid Vapor-phase Doping (RVD)Published by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Ultra-Shallow Buried-Channel P-MOSFET With Extremely High TransconductancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Design Methodology Of Deep Submicron CMOS Devices For 1V OperationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- High Performance 0.1/spl mu/m nMOSFET's with 10 ps/stage Delay (85 K) at 1.5 V Power SupplyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993