An engineering model for short-channel MOS devices
- 1 August 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 23 (4) , 950-958
- https://doi.org/10.1109/4.346
Abstract
An engineering model for short-channel MOS devices which includes the effect of carrier drift velocity saturation is described. Based on a piecewise carrier drift velocity model, simplified expressions for the DC drain current I/sub D/, the small signal transconductance g/sub m/ and the output conductance g/sub ds/ in the saturation region are derived. For a given gate voltage, the expressions depend only on the threshold voltage V/sub T/ and the dimensions of the device, whose desired values are normally known.Keywords
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