CMOS-on-SOI ESD protection networks
- 1 January 1998
- journal article
- Published by Elsevier in Journal of Electrostatics
- Vol. 42 (4) , 333-350
- https://doi.org/10.1016/s0304-3886(97)00156-3
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applicationsIBM Journal of Research and Development, 1995
- A half-micron CMOS logic generationIBM Journal of Research and Development, 1995
- Double snapback in SOI nMOSFETs and its application for SOI ESD protectionIEEE Electron Device Letters, 1993
- C-MOS/SOS gate-protection networksIEEE Transactions on Electron Devices, 1978
- An improved input protection circuit for C-MOS/SOS arraysIEEE Transactions on Electron Devices, 1978
- C-MOS/SOS LSI input/Output protection networksIEEE Transactions on Electron Devices, 1978
- Design of ion-implanted MOSFET's with very small physical dimensionsIEEE Journal of Solid-State Circuits, 1974