Submicron super TFTs for 3-D VLSI applications
- 1 September 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 21 (9) , 439-441
- https://doi.org/10.1109/55.863104
Abstract
High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, g/sub max/=198 mS/mm and an I/sub dast/ of 0.3 mA//spl mu/m at V/sub g/-V/sub t/=1.5 V, with L/sub G/=0.4 /spl mu/m and t/sub ox/=110 /spl Aring/. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS.Keywords
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