Impact of gate workfunction on device performance at the 50 nm technology node
- 1 June 2000
- journal article
- Published by Elsevier in Solid-State Electronics
- Vol. 44 (6) , 1077-1080
- https://doi.org/10.1016/s0038-1101(99)00323-8
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- New Gate Electrodes for Fully-Depleted Soi/cmos; Tin and Poly Si-GePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET'sIEEE Electron Device Letters, 1997
- Tungsten Gate Technology for Quarter-Micron ApplicationJapanese Journal of Applied Physics, 1996
- Formation of low pressure chemically vapour deposited W thin film on silicon dioxide for gate electrode applicationThin Solid Films, 1994
- A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditionsSolid-State Electronics, 1994
- A comprehensive model for inversion layer hole mobility for simulation of submicrometer MOSFET'sIEEE Transactions on Electron Devices, 1991
- A new approach to verify and derive a transverse-field-dependent mobility model for electrons in MOS inversion layersIEEE Transactions on Electron Devices, 1989