Sequential logic optimization for low power using input-disabling precomputation architectures
- 1 March 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 17 (3) , 279-284
- https://doi.org/10.1109/43.700725
Abstract
No abstract availableThis publication has 14 references indexed in Scilit:
- Sequential circuit design using synthesis and optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SYCLOP: synthesis of CMOS logic for low power applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Guarded evaluation: pushing power management to logic synthesis/designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
- Automatic synthesis of low-power gated-clock finite-state machinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
- Power estimation methods for sequential logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995
- Transition density: a new measure of activity in digital circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- On average power dissipation and random pattern testability of CMOS combinational logic networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986