Effects of stress-induced mismatches on CMOS analog circuits
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 354-360
- https://doi.org/10.1109/vtsa.1995.524719
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- The Design And Calibration Of A Semiconductor Strain Gauge ArrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETs)Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Errors associated with the design, calibration and application of piezoresistive stress sensors in (100) siliconIEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, 1994
- Evaluation of piezoresistive coefficient variation in silicon stress sensors using a four-point bending test fixtureIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1992
- A new aspect on mechanical stress effects in scaled MOS devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- Strain-gauge mapping of die surface stressesIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989
- Shear Stress Evaluation of Plastic PackagesIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1987
- A graphical representation of the piezoresistance coefficients in siliconIEEE Transactions on Electron Devices, 1982
- Piezoresistive Properties of Heavily Doped-Type SiliconPhysical Review B, 1964
- Piezoresistance Effect in Germanium and SiliconPhysical Review B, 1954