Optimizing quarter and sub-quarter micron CMOS circuit speed considering interconnect loading effects
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 44 (9) , 1556-1558
- https://doi.org/10.1109/16.622616
Abstract
An experimentally confirmed accurate CMOS gate delay model is applied to the CMOS ring oscillators with interconnect loading. The optimum gate oxide thickness Tox should be chosen differently as interconnect loading varies. Guidelines in choosing optimum Tox for different interconnect loading, combined with channel length and power supply scaling, are obtainedKeywords
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