Dual depletion CMOS (D/sup 2/CMOS) static memory cell
- 1 August 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 12 (4) , 424-426
- https://doi.org/10.1109/JSSC.1977.1050924
Abstract
A new type of static memory cell-dual depletion CMOS (D/SUP 2/MOS)-has been designed and fabricated using SOS wafers by the conventional CMOS/SOS technology. In contrast to the conventional CMOS static memory cell, which comprises six transistors, the new cell consists merely of four transistors and one data-line so that the cell area can be significantly reduced.Keywords
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