On the design and test of asynchronous macros embedded in synchronous systems
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Using hierarchy in macro cell test assemblyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Hierarchical test generation using precomputed tests for modulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Macro Testing: Unifying IC And Board TestIEEE Design & Test of Computers, 1986
- On the models for designing VLSI asynchronous digital systemsIntegration, 1986
- A methodology for the fast and testable implementation of state diagram specifications [logic design]IEEE Journal of Solid-State Circuits, 1985
- Design for Testability—A SurveyIEEE Transactions on Computers, 1982
- Analysis of petri nets by stepwise refinementsJournal of Computer and System Sciences, 1979