A metallisation providing two levels of interconnect for beam-leaded silicon integrated circuits
- 1 August 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 12 (4) , 376-382
- https://doi.org/10.1109/JSSC.1977.1050917
Abstract
A two-level-metal structure is described for beam-leaded silicon integrated circuits. The two-level structure consists of a Ti-Pt first level, plasma-deposited silicon nitride as interlevel dielectric, and Ti-Pt-Au as a second level. The Ti-Pt layers of both levels are sputter deposited. Sputter etching is used for pattern definition of the Pt layer of the first level and the Pt-Au layers of the second level. Two examples are presented of the application of the structure to bipolar integrated circuits. One is a LSI circuit consisting of a 24/spl times/9-bit sequential access memory implemented in a Schottky I/SUP 2/L technology and the other is a seven-gate inverter implemented in a standard buried collector technology.Keywords
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