The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 37 (8) , 1842-1851
- https://doi.org/10.1109/16.57135
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- A high-performance sub-half micron CMOS technology for fast SRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A physical model for boron penetration through thin gate oxides from p/sup +/ polysilicon gatesIEEE Electron Device Letters, 1990
- The effect of fluorine in silicon dioxide gate dielectricsIEEE Transactions on Electron Devices, 1989
- Hot-electron hardened Si-gate MOSFET utilizing F implantationIEEE Electron Device Letters, 1989
- Subquarter-micrometer gate-length p-channel and n-channel MOSFETs with extremely shallow source-drain junctionsIEEE Transactions on Electron Devices, 1989
- Ambient and dopant effects on boron diffusion in oxidesApplied Physics Letters, 1986
- Design tradeoffs between surface and buried-channel FET'sIEEE Transactions on Electron Devices, 1985
- Experimental derivation of the source and drain resistance of MOS transistorsIEEE Transactions on Electron Devices, 1980
- Redistribution of Acceptor and Donor Impurities during Thermal Oxidation of SiliconJournal of Applied Physics, 1964