Distortion compensation of multi-MESFET circuits
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 5, 189-192 vol.5
- https://doi.org/10.1109/iscas.1994.409335
Abstract
We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimise 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analysed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearised Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies.<>Keywords
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