A 45ns 64Mb DRAM With A Merged Match-line Test Architecture
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 3 references indexed in Scilit:
- A novel stacked capacitor cell with dual cell plate for 64 Mb DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A 1.5 V circuit technology for 64 Mb DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990