Enhancement of PMOS device performance with poly-SiGe gate
- 1 May 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 20 (5) , 232-234
- https://doi.org/10.1109/55.761024
Abstract
Poly-Si and poly-Si/sub 0.75/Ge/sub 0.25/-gated PMOS transistors with a very thin gate oxide of 29 /spl Aring/ were fabricated. In addition to reduced gate-depletion effect (GDE) and reduced boron penetration, more favorable I/sub d/-V/sub d/ characteristics were observed for the poly-SiGe-gated transistors than poly-Si-gated transistors. This and the underlying superior hole mobility are explained with a universal mobility model based on V/sub g/, T/sub ox/, V/sub th/ and V/sub th/. Both reduced GDE and superior hole mobility contribute to the enhanced performance.Keywords
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