The effect of interfacial traps on the stability of insulated gate devices on InP

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Abstract
Measurements of the change in channel current with time following application of a step voltage to the input of enhancement-mode insulated gate Field-Effect Transistors (FETs) on InP are reported. The data indicate that, following an initial steady-state period, the current varies exponentially with inverse temperature and logarithmically with time. This behavior suggests that a thermally activated tunneling process is responsible for the drift in these structures but leaves unanswered the question of the origin of the states responsible. It does appear, however, that, whereas its complete removal may be counterproductive, the proper preparation of the native oxide layer beween the InP and the deposited dielectric may be determinative in the establishment of a low-trap density interface.

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