Memory Interference Models with Variable Connection Time

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Abstract
This correspondence develops two discrete memory interference models. These models, the equivalent rate model and the Markov chain model, provide for variable connection times between processors and memories if these times can be characterized by a discrete random variable X. The equivalent rate model, which is the simpler, requires only the first moment of X, while the Markov chain model requires the first and second moments. The models yield estimates of the bandwidth BW, the probability of acceptance Pa, and processor utilization Up. Both models give good estimates of BW when the coefficient of variation Cv of X is small. When Cv reaches 2.0 the Markov chain model still shows an error of less than 4 percent while the equivalent rate model exhibits a 50 percent error that, unlike the Markov chain model, continues to increase with increase in Cv. Finally, it is shown that BW drops significantly with increase in Cv. suggesting that processor-memory transfers should use a fixed block size if memory conflict is to be minimized.

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