A fault oriented partial scan design approach
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An economical scan design for sequential logic test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An incomplete scan design approach to test generation for sequential machinesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- HITEC: a test generation package for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An optimization based approach to the partial scan design problemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On determining scan flip-flops in partial-scan designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- BALLAST: a methodology for partial scan designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- Controllability/observability analysis of digital circuitsIEEE Transactions on Circuits and Systems, 1979
- Depth-First Search and Linear Graph AlgorithmsSIAM Journal on Computing, 1972