Automated synthesis for testability
- 1 May 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Industrial Electronics
- Vol. 36 (2) , 263-277
- https://doi.org/10.1109/41.19078
Abstract
The authors present an integrated, compiler-driven approach to digital chip design that automates mask layout and test-pattern generation for 100% stuck-at fault coverage. This approach is well suited for designs where it is most important the minimize the design cycle time rather than the silicon area. The authors show that by compiling from a unified design specification followed by logic synthesis it is possible to reduce the problem of automatic test-pattern generation. They present a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques. A section on benchmark results highlights the close coupling of a language-based design specification, logic synthesis, and testability.<>Keywords
This publication has 25 references indexed in Scilit:
- Synthesis from VHDLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Boundary scan with cellular-based built-in self-testPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Advanced automatic test pattern generation and redundancy identification techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An automated BIST approach for general sequential logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SOCRATES: a highly efficient automatic test pattern generation systemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Testability-Driven Random Test-Pattern GenerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Accelerated Fault Simulation and Fault Grading in Combinational CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- A hierarchical approach test vector generationPublished by Association for Computing Machinery (ACM) ,1987
- DAGON: technology binding and local optimization by DAG matchingPublished by Association for Computing Machinery (ACM) ,1987